The present invention relates to semiconductor integrated circuit devices and, more particularly, to a technique which is effectively applied primarily to power supplying techniques for dynamic RAMs (random access memories).
In order to increase the information retention time of memory cells of a dynamic RAM, the impurity concentration of the substrate must be reduced to reduce the electric field of a p-n junction formed between source and drain diffusion layers of a MOSFET for address selection and the substrate. Such a reduction of the substrate impurity concentration results in a decrease of the threshold voltage of the MOSFET, which in turn results in an increase in the leakage current between the source and drain when the gate voltage is at a non-select level, such as ground potential. As a solution to this problem, it has been proposed to set the non-select level of word lines to which a gate is connected at a negative voltage. The negative voltage is obtained using a charge pump circuit and is stabilized by controlling an oscillation circuit for providing an intermittent oscillation with a level sensor. Examples of dynamic RAMs in which the non-select level of the word lines is set at a negative voltage to improve the information retention time are disclosed in Japanese unexamined patent publications No. H2-5290, No. H6-255566, No. H7-57461 and No. H7-307091.
A substrate voltage undergoes a relatively significant potential fluctuation, e.g., in the range from 10 to 30%, attributable to capacitive coupling between bit lines and word lines and itself when the bit lines and word lines undergo level changes between select and non-select levels. It has therefore been found that, when it is attempted to use a negative back bias voltage supplied to a substrate voltage by a charge pump circuit as the non-select level of word lines, as described above, discharge is caused by capacitive coupling as described above, and a current flows to pull the select level of the word lines to the non-select level, and so the discharge can cause a temporary shortage of the non-select level of the word line, which is a major cause of deterioration of information retention characteristics. In order to solve this problem, improvements in the internal power supply circuits were pursued to allow them to operate with stability.
It is therefore an object of the invention to provide a semiconductor integrated circuit device having an internal power supply circuit which operates with stability. It is another object of the invention to provide a semiconductor integrated circuit device including a dynamic RAM which has an increased storage capacity and improved information retention characteristics. It is still another object of the invention to provide a semiconductor integrated circuit device which has higher reliability and operating speed and lower power consumption. The above-described and other objects and novel features of the invention will become more clear from the description in this specification and from the accompanying drawings.
According to the invention, there is provided a semiconductor integrated circuit comprising a first circuit block operating on a power supply voltage supplied through an external terminal and a second circuit block operating on an internal voltage generated by a power supply circuit, in which the internal voltage is generated by generating a voltage having a greater absolute value than that of the internal voltage using a charge pump circuit, and in which variable impedance means is provided between the output voltage and the internal voltage and the variable impedance means is controlled to compare and cause a reference voltage and the internal voltage to agree with each other using a differential amplifier circuit operating on the output voltage generated by the charge pump circuit.